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Clock gating

Technique used in synchronous circuits for reducing dynamic power dissipation, by adding more logic to a circuit to prune the clock tree (disabling portions of the circuitry so that the flip-flops in them do not have to switch states)

In computer architecture, clock gating is a popular power management technique used in many synchronous circuits for reducing dynamic power dissipation (a significant source of power dissipation in digital designs), by removing the clock signal when the circuit, or a subpart of it, is idle. Clock gating saves power by pruning part of the clock tree distribution, at the cost of adding more logic to a circuit.

From Wikipedia

In computer architecture, clock gating is a popular power management technique used in many synchronous circuits for reducing dynamic power dissipation (a significant source of power dissipation in digital designs), by removing the clock signal when the circuit, or a subpart of it, is idle. Clock gating saves power by pruning part of the clock tree distribution, at the cost of adding more logic to a circuit. Pruning the clock turns off portions of the circuitry so that the flip-flops in them do not switch state, as switching the state consumes power. When not switched, the switching power consumption is reduced. This technique is particularly effective in systems with significant idle time or predictable periods of inactivity within specific modules.

Text: Wikipédia, CC BY-SA 4.0. · Image: Shinaimm (CC BY-SA 4.0) ·

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